This invention relates to a latch circuit for use in a synchronous memory which has an internal clock circuit for producing an internal clock signal for latching an address signal, a command signal, and a data signal in synchronization with an external clock signal and which inputs and outputs the address signal, the command signal, and the data signal in accordance with the internal clock signal. This invention also relates to the synchronous memory including the latch circuit.
For a latch circuit used in an existing synchronous memory such as a synchronous dynamic random access memory (SDRAM), a setup time and a hold time of an input signal, input and output pin capacitances, and input and output amplitudes are defined in detail in specifications so as to operate an input/output interface between an inside and an outside of a chip at a high frequency (i.e., a high speed). On the other hand, in order to increase an operation speed inside the chip, development of a finer process and a higher-speed device is effective, but it is difficult to follow up the high-frequency (high-speed) operation of the interface. Thus, a difference between the operation speed inside the chip and the operation speed at the interface tends to increase. Under the circumstances, a prefetch memory capable of reading and writing a plurality of bits of data in parallel is effective in order to increase the operation speed inside the chip.
As a typical prefetch memory, a double data rate synchronous dynamic random access memory (DDR-SDRAM) is known. The DDR-SDRAM transfers a data at a rising edge and a falling edge of an external clock, i.e., at a double data rate as compared with a synchronous operation in which a single data is transferred in one cycle of the external clock. In the DDR-SDRAM, the number of prefetch bits is equal to 2N where N represents the number of data pins (DQ). Thus, 2N-prefetch is achieved. Further, in a DDR2-SDRAM as an improvement of the DDR-SDRAM, data transfer is continuously carried out every two cycles of the external clock. In this case, the number of prefetch bits is equal to 4N. Thus, 4N-prefetch is achieved. By increasing the number of the prefetch bits as mentioned above, a data transfer rate is improved. In case of a 8-bit (×8) structure, N is equal to 8.
In the 2N-prefetch, 2×8 (=16) bits of data are read in parallel and outputted at two separate timings, i.e., in synchronization with the rising edge and the falling edge in each cycle of the external clock. Therefore, the 2N-prefetch allows an operating frequency inside the chip to be equal to ½ of an external clock frequency of the external clock. In the 4N-prefetch, 4×8 (=32) bits of data are read in parallel and outputted at four separate timings, i.e., in synchronization with the rising edges and the falling edges in every two cycles of the external clock. Therefore, the 4N-prefetch allows the operating frequency inside the chip to be equal to ¼. Thus, such a prefetch architecture is effective in increasing the operation speed inside the chip in conformity with the higher-frequency operation of the interface.
However, even if the prefetch architecture is used, it is impossible to increase an operation speed at a portion where an external input signal such as a command signal, an address signal, or a data signal is captured from the outside of the chip to the inside of the chip. The above-mentioned portion is implemented by a latch circuit and must have a clock frequency equal to the external clock frequency in order to enable the address signal, the command signal, or the data signal to be inputted and outputted in synchronization with the external clock. Therefore, an operating frequency of the synchronous memory is limited by a performance of the latch circuit even if the prefetch architecture is adopted.
Recently, the higher-frequency operation at the interface is achieved by lowering a power supply voltage from 2.5 V to 1.8V, further to 1.5 V, and narrowing an amplitude of the external input signal. Correspondingly, the operation speed inside the chip is increased by increasing the number of prefetch bits from 2N to 4N, further to 8N. Under the circumstances, the latch circuit is also required to be increased in operation speed in order to meet the higher-frequency operation at the interface.
Referring to FIGS. 1 through 3, an existing DDR2-SDRAM will be described. A command latch circuit 130 illustrated in FIGS. 1 and 2 comprises a command decoder 131, a latch circuit 132, and an output circuit 132. Various external command signals RASB, CASB, WEB, and CSB are captured into an internal circuit of the chip through the command decoder 131, the latch circuit 132, and the output circuit 133. The latch circuit 132 is supplied with an internal clock signal CLKB as a control signal for latching.
As shown in FIG. 3, the internal clock signal CLKB synchronized with all rising edges of an external clock signal CK is supplied to the latch circuit 132. Therefore, the external clock signal CK and the internal clock signal CLKB are equal in operating frequency to each other. Thus, the command latch circuit 130 comprises a latch circuit 132 corresponding to the internal clock signal CLKB and is operable at the operating frequency equal to an external clock frequency of the external clock signal CK.
For a standard data transfer rate of 667 Mbps of the DDR2-SDRAM, the external clock signal CK has a frequency period (TCK) of 3 ns. In this case, the internal clock signal CLKB has a pulse width as small as about 1.5 ns which corresponds to a half of that in the DDR-SDRAM having a data transfer rate of 333 Mbps. Therefore, without a significant improvement such as achievement of a finer process and a higher-speed device, it is difficult to reserve a sufficient margin in capturing or fetching the command signal. In this event, an operation error may be caused to occur due to an insufficient margin.
As a result, the operating frequency inside the chip is limited by the performance of the latch circuit. Even in the prefetch architecture is adopted, a high-frequency memory is difficult to achieve. Further, a high-frequency operation inside the latch circuit deteriorates setup and hold characteristics.